Advanced model order reduction techniques in VLSI design / (Record no. 522543)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03042nam a22003498i 4500 |
| 001 - CONTROL NUMBER | |
| control field | CR9780511541117 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | UkCbUP |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200124160331.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION | |
| fixed length control field | m|||||o||d|||||||| |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr|||||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 090501s2007||||enk o ||1 0|eng|d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780511541117 (ebook) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Cancelled/invalid ISBN | 9780521865814 (hardback) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Cancelled/invalid ISBN | 9781107411548 (paperback) |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | UkCbUP |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | UkCbUP |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7874.75 |
| Item number | .T36 2007 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| Edition number | 22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Tan, Sheldon X. D., |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Advanced model order reduction techniques in VLSI design / |
| Statement of responsibility, etc | Sheldon X.-D. Tan, Lei He. |
| 264 #1 - Production, Publication, Distribution, Manufacture, and Copyright Notice (R) | |
| Place of production, publication, distribution, manufacture (R) | Cambridge : |
| Name of producer, publisher, distributor, manufacturer (R) | Cambridge University Press, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2007. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (xviii, 240 pages) : |
| Other physical details | digital, PDF file(s). |
| 336 ## - Content Type (R) | |
| Content type term (R) | text |
| Content type code (R) | txt |
| Source (NR) | rdacontent |
| 337 ## - Media Type (R) | |
| Media type term (R) | computer |
| Media type code (R) | c |
| Source (NR) | rdamedia |
| 338 ## - Carrier Type (R) | |
| Carrier type term (R) | online resource |
| Carrier type code (R) | cr |
| Source (NR) | rdacarrier |
| 500 ## - GENERAL NOTE | |
| General note | Title from publisher's bibliographic system (viewed on 05 Oct 2015). |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | List of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Integrated circuits |
| General subdivision | Very large scale integration |
| -- | Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | He, Lei, |
| Relator term | author. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Print version: |
| International Standard Book Number | 9780521865814 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1017/CBO9780511541117">https://doi.org/10.1017/CBO9780511541117</a> |
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