000			02214nam a22003498i 4500
001			CR9780511607059
003			UkCbUP
005			20200124160253.0
006			m|||||o||d||||||||
007			cr||||||||||||
008			090910s2005||||enk o ||1 0|eng|d
020			_a9780511607059 (ebook)
020			_z9780521828666 (hardback)
020			_z9780521045728 (paperback)
040			_aUkCbUP _beng _erda _cUkCbUP
050	0	0	_aTK7885.7 _b.L55 2005
082	0	0	_a621.39/2 _222
100	1		_aLilja, David J., _eauthor.
245	1	0	_aDesigning digital computing systems with Verilog / _cDavid J. Lilja and Sachin S. Sapatnekar.
264		1	_aCambridge : _bCambridge University Press, _c2005.
300			_a1 online resource (ix, 160 pages) : _bdigital, PDF file(s).
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
500			_aTitle from publisher's bibliographic system (viewed on 05 Oct 2015).
520			_aThis book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.
650		0	_aVerilog (Computer hardware description language)
650		0	_aElectronic digital computers _xDesign and construction.
700	1		_aSapatnekar, Sachin S., _d1967- _eauthor.
776	0	8	_iPrint version: _z9780521828666
856	4	0	_uhttps://doi.org/10.1017/CBO9780511607059
999			_c519693 _d519691