000			02559nam a22003378i 4500
001			CR9780511626913
003			UkCbUP
005			20200124160309.0
006			m|||||o||d||||||||
007			cr||||||||||||
008			090916s2009||||enk o ||1 0|eng|d
020			_a9780511626913 (ebook)
020			_z9780521859721 (hardback)
040			_aUkCbUP _beng _erda _cUkCbUP
050	0	0	_aTK7874.58 _b.P73 2009
082	0	0	_a621.3815/48 _222
245	0	0	_aPractical design verification / _cedited by Dhiraj K. Pradhan, Ian G. Harris.
264		1	_aCambridge : _bCambridge University Press, _c2009.
300			_a1 online resource (xi, 276 pages) : _bdigital, PDF file(s).
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
500			_aTitle from publisher's bibliographic system (viewed on 05 Oct 2015).
505	0		_aModel checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva.
520			_aImprove design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).
650		0	_aIntegrated circuits _xVerification.
700	1		_aPradhan, Dhiraj K., _eeditor.
700	1		_aHarris, Ian G., _eeditor.
776	0	8	_iPrint version: _z9780521859721
856	4	0	_uhttps://doi.org/10.1017/CBO9780511626913
999			_c520946 _d520944